The present invention relates to a microprogram control apparatus in an information processing apparatus and, more particularly, to a control memory error correcting apparatus having functions of detecting/correcting an operation of a correctable error and inhibiting an operation of an operation unit during an error detection.
A conventional example will be described below with reference to the accompanying drawings.
FIG. 4 shows an arrangement of the conventional microprogram control apparatus. Referring to FIG. 4, a microinstruction is stored in a control memory 21. This microinstruction is constituted by the following components: an address field A representing next address information; an arithmetic control field B for causing a pattern of the microinstruction to directly control an arithmetic circuit 25; a control pattern field C for generating a control pattern of an arithmetic circuit 26; and an error correcting code according to a Hamming code given to a series of bit patterns. The microinstruction read out from the control memory 21 is stored in a microinstruction register 22.
The control pattern field C of the microinstruction stored in the microinstruction register 22 is input to a control pattern generator 23. The control pattern generator 23 generates a control pattern in accordance with the microinstruction represented by the control pattern field C, and inputs/stores it in a control pattern storage register 24. The control pattern storage register 24 outputs the stored control pattern to the arithmetic circuit 26 to control it. Two typical methods of generating a control pattern will be shown below with reference to FIGS. 6 and 7. FIG. 6 shows a hardware decoding method for causing a decoder 72 to decode a second field of a microinstruction, thereby obtaining a control pattern. FIG. 7 shows a RAM decoding method of obtaining a control pattern from a control pattern memory 73 by using the second field of the microinstruction as an address. By using the above methods, the control pattern can be obtained. The arithmetic circuit 26 stores an arithmetic result in an arithmetic result register 30.
The arithmetic control field B of the microinstruction stored in the microinstruction register 22 is input to the arithmetic circuit 25. The arithmetic circuit 25 performs the operation in accordance with the microinstruction represented by the arithmetic control field B, and inputs/stores the arithmetic result in an arithmetic result storage register 29. Note that the arithmetic circuit 25 and the arithmetic result storage register 29 constitute an operation unit 33, and the arithmetic circuit 26 and the arithmetic result storage register 30 constitute an operation unit 34.
If error detectors 271 to 273 in an operation inhibit signal generator 27 detect errors in any of the address field A, the arithmetic control field B, and the control pattern field C of the microinstruction stored in the microinstruction register 22, the detectors 271 to 273 generate an operation inhibit signal D through an OR circuit 274 and inhibit the updating of the control pattern storage register 24 and the arithmetic result storage registers 29 and 30 in the operation units 33 and 34. Therefore, these registers are not adversely affected by the microinstruction including the errors. The error correction circuit 28 corrects the error of the microinstruction and stores it in the microinstruction register 22 during the generation of the operation inhibit signal.
A series of the above operations will be described below with reference to the timing chart shown in FIG. 5. When an error-including microinstruction Ei' is stored in the microinstruction register 22, the operation inhibit signal D is generated, updating of the control pattern storage register 24 and the arithmetic result storage registers 29 and 30 is inhibited, and the registers 24, 29 and 30 respectively keep holding data F1.sub.i-1, R1.sub.i-1 and R2.sub.i-2. An error-corrected microinstruction Ei is stored in the microinstruction register 22 in the next clock cycle. The operation inhibit signal D is canceled and a normal operation restarts. Therefore, operations of the control pattern storage register 24 and the arithmetic result storage registers 29 and 30 are not adversely affected by the microinstruction Ei' and can be properly performed.
In the control memory error correcting apparatus of this type, the correctable error is detected in all fields of the microinstruction and the updating of the control pattern storage register 24 and the arithmetic result storage registers 29 and 30 in the operation units 33 and 34 is inhibited in an error-detected clock cycle.
In the conventional control memory error correcting apparatus as described above, the correctable error is detected in all fields of the microinstruction and the operation of the operation units is inhibited in an error-detected clock cycle.
A microprogram control apparatus, generally, comprises a plurality of LSIs. Some LSIs are arranged near an arithmetic circuit, and some LSIs are arranged away from an arithmetic circuit. The microinstruction register is realized by the plurality of LSIs in a distributed manner. For this reason, when an error is detected in all the fields of the microinstruction and the operation inhibit signal D is generated, the delay time of the operation inhibit signal D during its propagation from the microinstruction register 22 of the remote LSI to the control pattern storage register 24 and the arithmetic result storage registers 29 and 30 is prolonged. Therefore, the clock cycle is also prolonged.